Certain non-volatile memory devices may operate by trapping charges in a dielectric interface to adjust the threshold voltage of a transistor and thus program the desired digital value of the transistor. One method of trapping charges is found in nonvolatile flash devices that use a floating gate electrode layer placed between a tunnel oxide layer and a control oxide layer to trap charges under the influence of a control gate electrode.
Such non-volatile memory devices may have a reliability problem with controlling current carrier flow through the dielectric layers from electrode to electrode due to the very thin physical thickness of the dielectric layers used to obtain rapid current flow at reasonable voltage levels. For example, in a floating gate memory the top and bottom surfaces of each insulator layer may be in contact with a conductive surface since each insulator layer may be located between solid conductive electrodes such as the substrate, the floating gate, and the control gate. Thus, a defect in either insulator layer may cause a device failure in a floating gate device. Charge trapping type non-volatile devices such as NROMs and NMOS devices use a change in dielectric properties to create a layer of charge carriers, typically with an oxide-nitride-oxide (ONO) arrangement of three dielectric layers. This arrangement is less sensitive to dielectric defects in one of the three dielectric layers, but may have an issue with the programming and erasing voltage levels used to obtain reasonable read and write speeds. It may also be difficult to obtain smooth surfaces with the tendency of each one of three dielectric depositions to accentuate the particles and non-uniformities of the previous layer, which may result in electric field concentration and increased time dependent dielectric breakdown.
The above noted issues of dielectric defect levels may become even more of an issue in the future, since the semiconductor device industry has a need to continue to reduce the size of semiconductor devices such as transistors to obtain lower power consumption and higher performance. In general, to reduce transistor size, the thickness of the silicon dioxide (SiO2) gate dielectric is reduced in proportion to the shrinkage of the gate length. For example, a metal-oxide-semiconductor field effect transistor (MOSFET) might use a 1.5 nm thick SiO2 gate dielectric for a gate length of 70 nm. An industry goal is to fabricate smaller, more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
The semiconductor industry relies on the ability to reduce the dimensions of its basic devices, generally known as scaling, to increase performance, decrease power consumption, and decrease product costs, for example the silicon based MOSFET. This device scaling includes scaling the gate dielectric, which has primarily been fabricated using silicon dioxide. This is because thermally grown amorphous SiO2 layer provides an electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. However, increased scaling and other requirements in microelectronic devices have indicated a need to use other dielectric materials as gate dielectrics, in particular dielectrics with higher dielectric constants (high-k) to replace the use of various combinations of SiO2, Si3N4 and SiON. For these higher dielectric constant materials to be practical they must have the properties of high permittivity, thermal stability, high film and surface quality and smoothness, hysteresis characteristics, leakage current density, and long term reliability.
High-k layers may be formed of metal oxide unary materials such as Al2O3, CeO2, HfO2 and ZrO2, which have a single metallic component. High-k dielectric layers may be formed as binary systems such as (Y2O3)x(ZrO2)1-x, LaAlO3, and (HfO2)(Al2O3), which have two metallic components, and so on. High-k layers may be formed in single layers, or may be formed of multiple layers of different materials that act as a composite material. The high-k materials are preferably in an amorphous state, which may result in better surface smoothness (which may reduce electric field concentration at sharp projections), and may reduce leakage current along crystal boundaries. Thus, there is a need in the industry to form high-k layers that possess the above noted features and are practical for use in manufacturing integrated circuits (ICs).